SPI1 control register.
| SPI_MEM_FDUMMY_RIN | In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. |
| SPI_MEM_FDUMMY_WOUT | In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. |
| SPI_MEM_FDOUT_OCT | Apply 8 signals during write-data phase 1:enable 0: disable |
| SPI_MEM_FDIN_OCT | Apply 8 signals during read-data phase 1:enable 0: disable |
| SPI_MEM_FADDR_OCT | Apply 8 signals during address phase 1:enable 0: disable |
| SPI_MEM_FCMD_QUAD | Apply 4 signals during command phase 1:enable 0: disable |
| SPI_MEM_FCMD_OCT | Apply 8 signals during command phase 1:enable 0: disable |
| SPI_MEM_FCS_CRC_EN | For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. |
| SPI_MEM_TX_CRC_EN | For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable |
| SPI_MEM_FASTRD_MODE | This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. |
| SPI_MEM_FREAD_DUAL | In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. |
| SPI_MEM_RESANDRES | The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. |
| SPI_MEM_Q_POL | The bit is used to set MISO line polarity, 1: high 0, low |
| SPI_MEM_D_POL | The bit is used to set MOSI line polarity, 1: high 0, low |
| SPI_MEM_FREAD_QUAD | In the read operations read-data phase apply 4 signals. 1: enable 0: disable. |
| SPI_MEM_WP | Write protect signal output when SPI is idle. 1: output high, 0: output low. |
| SPI_MEM_WRSR_2B | two bytes data will be written to status register when it is set. 1: enable 0: disable. |
| SPI_MEM_FREAD_DIO | In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. |
| SPI_MEM_FREAD_QIO | In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. |